During the last decade, researchers realized that increasing transistors to microprocessor in order to increase clock rate is not the solution to increase applications performance rather focusing on research optimize programming models and effective use of microprocessor will be the better solution. The increase in Power/Density ratio of microprocessors is leading towards the situation from where there will be no way to resolve heat dissipation.
One solution can be utilizing specialized hardware dedicated to accelerate specific applications of system which is known as heterogeneous processing; for example, GPUs for graphics applications, DSPs for complex mathematical applications, FPGAs for performance critical applications, Intel Microprocessors for general purpose computing. Although, accommodating specific hardware for specific application provides high performance with better power efficiency. In return heterogeneous systems become difficult to program, mostly because of taking care of managing data flow between different architectural processors from the execution point of view.
Other one is known as homogeneous processing consisting processors of the same architecture. In multi-processing, processors work together in tightly coupled manner in order to process one or more jobs simultaneously. All processors have strong connection to each other by sharing common clock, instruction set etc. By increasing processors never create any problem for the designer due to same architecture pattern. Multi-processors increased reliability of the system, if one of the processor goes down then load is transferred or shared between other processors. On the other hand, in heterogeneous systems it will be complete shutdown of the system.
In order to achieve optimum performance of the system, we need architecture which is capable of accommodating both heterogeneous and homogeneous processing units. Multiple processing usages are becoming essential part of the embedded systems development nowadays. While considering multi-core architectural pattern, each core can be dedicated to perform certain specific task. The important task is to plan and map work load on different cores need to be done before writing algorithms. This article is to explain one of the Multi-core Architecture Simulator (SESC) and Multicube Explorer which helps the designer in order to explore design space of multi-core architecture.
SESC Simulator:
Simulator or Architectural Simulator is basically a software model which actually replicates actual hardware/software resources of the actual system. The core purpose of simulator is to predict system behavior and performance metrics relevant to specific inputs. This Architectural Simulator can either model microprocessor or complete system consists of microprocessor, memory, and I/O devices.
SESC is one of the architectural simulators that can model different processor architectures, such as single processors, chip multi-processors and processors-in-memory. It models a full out-of-order pipeline with branch prediction, caches, buses, and every other component of a modern processor necessary for accurate simulation. SESC is an event-driven simulator. It has an emulator built from MINT, an old project that emulates a MIPS processor. Many functions in the core of the simulator are called every processor cycle. But many others are called only as needed, using events.
More information about SESC Simulator is available on http://sesc.sourceforge.net/. SESC project started at University of Illinois at Urbana‐Champaign.
Multicube Explorer:
Multicube explorer is an interactive program that lets the designer explore a design space of configurations for a parameterized architecture for which an executable model (use case simulator) exists. Multicube explorer is an advanced multi-objective optimization framework which is entirely command-line/script driven and can be re-targeted to any configurable platform by writing a suitable XML design space definition file and providing a configurable simulator. Multicube Explorer is supported by the EC under grant FP7-216693 MULTICUBE (http://www.multicube.eu).
The tool and the documentation can be currently found at the following address: http://home.dei.polimi.it/zaccaria/multicube_explorer.
Integration files required for design space exploration of SESC Simulator consist of:
- Python Script: The script used for generating of input/output configuration file of the SESC Simulator.
- XML Driver: Design space exploration file.
- Multicube Script: The m3explorer script file which actually automated the exploration process.
- Shell Script: The shell script which automates the whole integration process of SESC Simulator and Multicube Explorer.
Hi
ReplyDeleteI have an idea to improve the method witch R Teodorescu et Al offer in this paper:
"Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors"
using SESC. But I'm new to SESC and I don't know where to start and how to use SESC to do so?
I hope I can use your experiments and point of views.
thanks
hesam