Saturday, June 19, 2010

Intelligently Present Info Screen (IPIS) [Human Computer Interaction]

Abstract

The IPIS (Intelligently Present Info Screen) application will guide a user to find important places, important persons, ongoing cultural events, moral stories and histories of a place and talent hunt events. Application will show user current location automatically in a map. It will indicate important places, persons, cultural activities and moral stories & histories in a map which are closest to user current position. Suppose users are in Duomo, Milan, Italy, application will suggest users “Roman Catholic” as a historical place showing in map to visit that place. Also in application user can tag places, important persons, cultural events and moral stories. General user or foreigner who want to search for a particular place or want to join in local cultural activities, application will help them. Application will show available transportation, shortest path and brief history of that place if available. Moral histories, user experience and comment will preserved by this application. This will be a digital preserve system where user can share each other experiences. User can broadcast their talent in a second. Application will help users to participate in a talent hunt event remotely .Suppose user current position is Milan and talent hunt event is ongoing in USA, Hollywood then user will perform in front of i-phone and that will be shown in a TV screen in talent hunt event in front of judge for judgment. Now if user want to move Milan to Rome and want to visit some tourist places on the way, application will guide them and draw road map according to tourist places. This application will be integrated with i-phone’s existing application.

Friday, June 18, 2010

Customized Function Module Integration in PerLa for WSNs

Abstract

PerLa or Pervasive System language is a declarative language for application in pervasive computing. This concept behind PerLa is to provide the user with the opportunity to manage heterogeneous pervasive devices while avoiding the complexity of underlying hardware. At present, PerLa provides the users with a declarative approach towards the network to be managed. However, a limitation which arose with increase of applicability of the language was the absence of any mechanism to induct customized user functions to perform need-based operations on the data e. g. filtering operations, performing statistical functions on the data and special-case procedural code inductions. In this report, we propose a way to introduce the possibility of integrating procedural functions in the existing declarative approach offered by PerLa. In order to allow for this approach, it is necessary to embed the custom-code in the system such that the existing architecture is disturbed at a minimum and maximum functionality is achieved. We present the solution in which the system capabilities can be extended with the design point of view. The implementation of these functionalities is separated from the design phase, covered in this report.

Saturday, June 5, 2010

SESC: Design Space Exploration of Architectural Simulators using MulticubeExplorer

During the last decade, researchers realized that increasing transistors to microprocessor in order to increase clock rate is not the solution to increase applications performance rather focusing on research optimize programming models and effective use of microprocessor will be the better solution. The increase in Power/Density ratio of microprocessors is leading towards the situation from where there will be no way to resolve heat dissipation.
One solution can be utilizing specialized hardware dedicated to accelerate specific applications of system which is known as heterogeneous processing; for example, GPUs for graphics applications, DSPs for complex mathematical applications, FPGAs for performance critical applications, Intel Microprocessors for general purpose computing. Although, accommodating specific hardware for specific application provides high performance with better power efficiency. In return heterogeneous systems become difficult to program, mostly because of taking care of managing data flow between different architectural processors from the execution point of view.
Other one is known as homogeneous processing consisting processors of the same architecture. In multi-processing, processors work together in tightly coupled manner in order to process one or more jobs simultaneously. All processors have strong connection to each other by sharing common clock, instruction set etc. By increasing processors never create any problem for the designer due to same architecture pattern. Multi-processors increased reliability of the system, if one of the processor goes down then load is transferred or shared between other processors. On the other hand, in heterogeneous systems it will be complete shutdown of the system.
In order to achieve optimum performance of the system, we need architecture which is capable of accommodating both heterogeneous and homogeneous processing units. Multiple processing usages are becoming essential part of the embedded systems development nowadays. While considering multi-core architectural pattern, each core can be dedicated to perform certain specific task. The important task is to plan and map work load on different cores need to be done before writing algorithms. This article is to explain one of the Multi-core Architecture Simulator (SESC) and Multicube Explorer which helps the designer in order to explore design space of multi-core architecture.

SESC Simulator:
Simulator or Architectural Simulator is basically a software model which actually replicates actual hardware/software resources of the actual system. The core purpose of simulator is to predict system behavior and performance metrics relevant to specific inputs. This Architectural Simulator can either model microprocessor or complete system consists of microprocessor, memory, and I/O devices.
SESC is one of the architectural simulators that can model different processor architectures, such as single processors, chip multi-processors and processors-in-memory. It models a full out-of-order pipeline with branch prediction, caches, buses, and every other component of a modern processor necessary for accurate simulation. SESC is an event-driven simulator. It has an emulator built from MINT, an old project that emulates a MIPS processor. Many functions in the core of the simulator are called every processor cycle. But many others are called only as needed, using events.

More information about SESC Simulator is available on http://sesc.sourceforge.net/. SESC project started at University of Illinois at Urbana‐Champaign.

Multicube Explorer:
Multicube explorer is an interactive program that lets the designer explore a design space of configurations for a parameterized architecture for which an executable model (use case simulator) exists. Multicube explorer is an advanced multi-objective optimization framework which is entirely command-line/script driven and can be re-targeted to any configurable platform by writing a suitable XML design space definition file and providing a configurable simulator. Multicube Explorer is supported by the EC under grant FP7-216693 MULTICUBE (http://www.multicube.eu).

The tool and the documentation can be currently found at the following address: http://home.dei.polimi.it/zaccaria/multicube_explorer.

Integration files required for design space exploration of SESC Simulator consist of:
  • Python Script: The script used for generating of input/output configuration file of the SESC Simulator.
  • XML Driver: Design space exploration file.
  • Multicube Script: The m3explorer script file which actually automated the exploration process.
  • Shell Script: The shell script which automates the whole integration process of SESC Simulator and Multicube Explorer.

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